1. Technical Field
The present application relates generally to an apparatus and method for providing an improved integrated circuit device. More specifically, the present application is directed to an apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip.
2. Description of Related Art
In the manufacture and testing of integrated circuit chips, a common technique is to form a wafer of semi-conductive material, such as silicon, and to form in and on the wafer the necessary circuitry for a multiplicity of integrated circuit chips. The wafer is formed with all of the circuitry necessary for the functioning of each of the chips, including I/O contacts for connecting to I/O signals, power and ground. The contacts may be for either wire bond connections or compressive bonding connections or for controlled collapse chip connect (C4) bonds which utilizes solder balls for flip chip bonding.
Whatever type of contact is to be made to the chip, it is necessary for the chip to be tested and a determination made as to whether the chip is good, i.e. operates correctly. This testing normally includes what is known as a “chip burn-in.” The burn-in process is intended to accelerate the early life of the integrated circuit chip so as to expose those chips that will fail. That is, it has been determined that the failure rate of integrated circuit devices is greatest at the beginning and end of the average life cycle of an integrated circuit chip. The relationship between failure rate of integrated circuits and time, both for testing and for application of end users, is usually referred to as a bathtub curve. An example of this bathtub curve is shown in FIG. 2.
As shown in FIG. 2, with the increase of time (period), the bathtub curve can be divided into an infant mortality period, a normal life period, and a wear out period. The infant mortality period usually corresponds to failure induced by defects of fabrication and usually lasts about several weeks. The normal life period usually corresponds to some random failures and usually lasts about twenty, thirty, or more years. The wear out period usually corresponds to failure induced by long-time waste and is continuously increased while time goes by.
The burn-in process is intended to accelerate the life of the integrated circuit chips through the infant mortality period to thereby identify which chips have fabrication defects and will fail. In order to perform such accelerated testing, a testing environment that is harmful and dangerous to the integrated circuit chips is generated by testing equipment and the relationship between the failure rate and testing time is measured. In order to generate the harmful testing environment, the chips are heated to an elevated temperature above which they are rated to function, and stressed by the application of voltage and current, also often in excess of what the chip is rated to withstand. The difference between the testing environment and a normal operating environment is used to estimate the relationship between failure rate and real time, which is the experienced time under the normal environment.
In the past, this burn-in process has normally taken place on the individual chips after the wafer has been diced to form the individual chips, often after the chips have been packaged. Thus, in the past, it was necessary to form the chips, individually handle the chips and test the chips individually, and only then were bad chips detected. An example of testing such chips is shown in commonly assigned U.S. Pat. No. 5,420,520, which is hereby incorporated by reference. While this type of testing does work well, it requires a significant amount of processing of the wafer following the formation of the circuitry on and in the wafer before a determination is made that a chip is indeed bad. Moreover, the device of U.S. Pat. No. 5,420,520, has a direct connection between the tester head and the chip. When the tester head connection is worn, the entire head must be discarded, or at least significantly reworked.
Commonly assigned U.S. Pat. No. 6,094,059, which is hereby incorporated by reference, provides an improved mechanism for performing burn-in/testing of integrated circuit chips that avoids the drawbacks of the mechanism described in U.S. Pat. No. 5,420,520. According to the mechanism in U.S. Pat. No. 6,094,059, a technique for testing/stressing integrated circuit devices, and especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. The technique includes providing an interposer, with the interposer including a dielectric substrate having a device contact face and a tester contact face. A first plurality of releasable connectors is provided on the device contact face arranged in the same predetermined pattern, and a second plurality of releasable connectors is provided on the tester contact face, also arranged in the same predetermined pattern. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head. The interposer is positioned between the IC device and the test head, with the contacts on the IC device in contact with the first plurality of connectors and the contact pads on the test head in contact with the second plurality of connectors.
Signals are provided to the connector pads from the electrical leads for performing testing and/or burn-in of the integrated circuit device. The test head can be heated to provide the necessary heat for testing at elevated temperatures, although preferably the entire assembly of the test head, interposer and IC device is placed in an oven which is heated to a controlled temperature, at which point the electrical testing signals are provided from an external source. The oven itself, in some instances, may be provided with outlets to connect with the electrical leads, thus connecting the leads to the exterior of the oven for the reception of the electrical signals.
Regardless of the particular mechanisms used to perform the burn-in process, be it the mechanism in U.S. Pat. No. 5,420,520, U.S. Pat. No. 6,094,059, or another mechanism, burn-in parameters used to control the burn-in process are set and run at the chip level. Thus, the entire chip is burned-in using the same temperature and voltage parameters.
Modern multi-core (or multiprocessor) microprocessor integrated circuit chips require separate voltage planes for each processor core in order to optimize performance of the cores (or processors). As the number of cores grows, so do the number of voltage planes that are needed in the integrated circuit chip. This leaves the architect two choices using today's technology: (1) keep adding voltage planes which increase the wiring needed for each part on the chip, package and board, as well as the amount of voltage regulator modules (VRMs) on the board; or (2) use one voltage plane for the multicore processors. The second option is less expensive, however it sub-optimizes the performance of the part for the cores that need a different voltage from the main voltage provided by the one voltage plane in order to perform at an optimum speed.
If a known burn-in process is applied to an integrated circuit chip using the single voltage plane approach discussed above, the burn-in is performed using chip level burn-in parameters. Thus, the same voltage and temperature is applied to all of the cores. Therefore, even after burn-in, the cores may still operate at sub-optimal speed due to the single voltage plane and the different voltage requirements of the various cores for running at speed.